© W. Yang et al., Published by EDP Sciences, 2026

1 Introduction

Numerical control drilling is a critical process in PCB manufacturing, and its processing time directly impacts production efficiency. Optimizing the drilling path can significantly reduce the non-cutting travel distance, thereby shortening the total processing time, improving efficiency, and reducing costs [1]. The PCB drilling path optimization problem is essentially a variant of the Traveling Salesman Problem (TSP) [2,3]. In recent years, researchers have proposed various solution methods: Nearest Neighbor [4] and Insertion methods [5] offer high computational efficiency and are commonly used to generate initial paths, but the quality of their solutions is often limited. Metaheuristic algorithms such as Genetic Algorithms (GA) [6], Simulated Annealing (SA) [7], and Ant Colony Optimization (ACO) [8] typically yield better paths through more in-depth search mechanisms, but their computational complexity increases significantly with problem size.

Notably, most existing studies treat all drilling points on a PCB as a homogeneous and randomly distributed whole for optimization. While this approach is generalizable, it largely overlooks the inherent layout features commonly found in PCB designs, such as the presence of multiple identical or similar modular units on the board, where hole positions exhibit distinct clustering and repetitive patterns [9]. This feature-agnostic optimization strategy not only leads to a sharp increase in computational resources as the number of holes grows but also fails to fully utilize design knowledge to guide the search, thereby limiting the efficiency of the algorithm and the quality of solutions.

For large-scale TSP problems, the concepts of hierarchical optimization and partition-based clustering have been successfully applied in fields such as logistics distribution and path planning [10–12]. The core idea lies in decomposing the problem, transforming global search into multiple subproblems of local optimization and global coordination, thereby effectively reducing solution complexity. In the field of PCB drilling path optimization, some scholars have begun exploring similar approaches. For example, one study proposed a partitioned adaptive ant colony algorithm to optimize the machining path of a specific CNC drilling machine. Simulation results showed its performance was superior to the standard algorithm, but the generalizability of the method requires further verification [13]. Ma [14] optimized ACO parameters through orthogonal experiments, achieving a 6% reduction in path length, but did not delve into the clustering characteristics of hole groups. Peng [15] noticed the layout features of PCBs and studied grouping and connection strategies, but their method lacked robustness considerations for non-ideal layouts, such as inconsistent hole group paths or irregular distributions.

In summary, current research exhibits the following significant gaps: First, there is a lack of a systematic framework capable of automatically identifying and utilizing the modular, repetitive, and other layout features prevalent in PCB designs. Second, within hierarchical optimization, how to intelligently determine partitioning strategies, optimize paths within subclusters, and efficiently connect paths between subclusters requires further in-depth research. Third, existing methods mostly target ideal, regular layouts, while their adaptability and optimization effectiveness remain unclear when dealing with the complex scenarios commonly encountered in actual production, which are often characterized by irregular and heterogeneous subclusters.

To address these issues, this study proposes a hybrid hierarchical optimization framework. The innovation of this framework is primarily reflected in three aspects: First, it introduces an automated layout feature extraction and partition clustering mechanism, enabling the algorithm to adaptively identify the modular aggregation characteristics of PCB hole positions. Second, it constructs a “global-local” two-tier optimization structure, employing improved metaheuristic algorithms for fine-grained optimization of each subcluster at the local level and designing efficient inter-cluster connection strategies at the global level. Finally, by integrating intelligent entry/exit point selection and 2-opt local search, it further optimizes the path connection quality both within and between subclusters. This study aims not only to enhance optimization efficiency under standard layouts but also to ensure the robustness of the algorithm under complex, non-ideal layouts. It is worth noting that the individual techniques of feature recognition, clustering, region optimization, and 2-opt refinement are not original contributions of this research. The fundamental innovation of this study lies in proposing a new “feature-driven, hierarchical optimization” framework specifically for PCB drilling.

The subsequent chapters are organized as follows: Chapter 2 constructs a mathematical model for the PCB drilling path optimization problem and clearly defines layout features. Chapter 3 elaborates in detail on the proposed hybrid hierarchical optimization algorithm based on layout features. Chapter 4 comprehensively validates the performance of the proposed algorithm through multiple sets of simulation experiments and comparisons with existing typical algorithms. Chapter 5 summarizes the entire study and outlines directions for future research.

2 Drilling path optimization modeling and analysis

2.1 Mathematical formulation of the drilling path optimization problem

The objective of drilling path optimization is to find the shortest path for the drill to visit all hole locations, thereby minimizing the non-cutting movement time between holes. By treating all machining holes as cities, the path planning task is transformed into a combinatorial optimization problem in mathematics. The fundamental components are as follows.

Treat each hole to be drilled as a city to be visited. Let the set of all hole locations be denoted as

$$V=\{v_0,v_1,v_2,\dots ,v_n\}$$(1)

where n represents the total number of holes, v₀ corresponds to the starting point of the machining process. The Euclidean distance from a hole v_i to another hole v_j is defined as d_ij, and the objective function can be defined as minimizing the total path length

$$\text{Min}{\displaystyle \sum _{i=1}^n{\displaystyle \sum _{j=1}^n{d}_{ij}{x}_{ij}}}$$(2)

where x_ij is a binary variable indicating whether the drill bit moves from drilling point v_i to drilling point v_j. As the problem size increases, the solution space grows combinatorially. The total number of possible paths is (n−1)!/2, which exhibits super-exponential growth.

2.2 Classification of layout features

In PCB design, engineers often arrange components and vias according to specific patterns to meet requirements such as circuit layout, signal integrity, thermal management, and mechanical fixation. Such intentionally introduced regularity during the design phase constitutes the layout features of a PCB. Traditional path optimization algorithms treat these elements as an unordered set of points, effectively overlooking the rich structural information embedded in the design. The core premise of this study is that recognizing and utilizing these features can decompose a large-scale, complex global optimization problem into multiple regular and more tractable subproblems. Common types of features include array patterns, module reuse and regional density characteristics.

Rectangular arrays are the most common type of array pattern, and their mathematical representation can be described as a parametric system. Let the reference origin coordinates of the array be (x₀, y₀), the number of rows be M, the number of columns be N, the row spacing be Δy, and the column spacing be Δx. Then, the coordinates of any hole in the array can be expressed as:

$$\{\begin{array}{c}{x}_{ij}=x_0+j\Delta x\\ y_{ij}=y_0+i\Delta y\end{array}\begin{array}{cc}& i\in [0,M-1],j\in [0,N-1]\end{array}.$$(3)

This type of array is commonly found in areas such as memory module slots, board-to-board connectors, and the bottom BGA packaging of FPGA chips. In practical designs, rectangular arrays may be incompletely filled, meaning certain positions within the array lack holes or mounting points. This increases the complexity of feature recognition, though the overall structure still maintains a distinct grid pattern.

Module reuse characteristics are based on an important observation: modern complex PCBs are often composed of multiple repeated subcircuit modules with identical functions. Mathematically, module reuse can be precisely described using affine transformations. For each hole position point in the original module, the set of hole positions for each reuse instance k can be expressed as:

$$P_k=\left\{T_k\left(v\right)|v\in V\right\}$$(4)

where, T_k is an affine transformation, typically involving basic transformations such as translation, rotation, mirroring, or their combinations. The most common scenario is a pure translation transformation, i.e., T_k(v) = v + v_k, where v_k is the translation vector. The algorithm only needs to perform fine-grained path optimization for one of the modules and then applies the optimized results to all other identical modules using the same transformation. In this way, a problem that originally required optimizing paths for n_module × n_holes hole positions (where n_module is the number of modules and n_holes is the number of holes per module) is transformed into optimizing paths for n_holes hole positions plus n_module module reference points.

3 Hybrid optimization algorithm design based on layout features

The hybrid optimization algorithm proposed in this study adopts a divide-and-conquer strategy. Its core idea is to decompose a large-scale global optimization problem into multiple smaller, more manageable local optimization subproblems, which are then integrated through a hierarchical structure. The overall framework of the algorithm follows a sequential processing flow, with its key steps illustrated in Figure 1.

Fig. 1 Algorithm framework diagram.

3.1 Feature extraction algorithm

The feature extraction algorithm in this study is based on the engineering specifications of PCB design, primarily aimed at identifying regular array patterns and module reuse features. By analyzing the spatial distribution of hole positions, the algorithm detects the presence of regular arrays defined by rows and columns. Specifically, for a given set of hole positions, it automatically identifies regular array patterns using known parameters such as unit size, number of horizontal units, number of vertical units, and unit spacing. First, the mathematical model of the array must be defined as follows:

$$\{\begin{array}{c}{x}_{ij}=j\cdot (S+D_x)+x_0+{\delta }_x\\ y_{ij}=i\cdot (S+D_y)+y_0+{\delta }_y\end{array}$$(5)

where (x₀,y₀) is the reference origin, δ_x and δ_y are manufacturing tolerances, D_x and D_y are the unit size, S is the unit spacing. This formula defines a virtual grid covering all or most of the hole positions. Then, by calculating the average positional offset between modules, potential repetitive patterns are quickly identified, providing the basis for the “optimize once, reuse multiple times” strategy in path optimization. Its core formula is:

$${\Delta }_{m,n}=({\overline{x}}_n-{\overline{x}}_m,{\overline{y}}_n-{\overline{y}}_m)$$(6)

where ${\Delta }_{m,n}$ represents the translation vector from module m to module n, indicating the overall positional offset relationship between the two modules. ${\overline{x}}_m,{\overline{y}}_m$ are the average coordinates of all hole positions in module m, defined according to the centroid coordinates. The physical meaning is that if ${\Delta }_{m,n}$ remains consistent or approximately equal across two different modules, and the hole position distributions within the modules are similar, it indicates that these modules may have been generated through the same translation transformation and belong to repeated design units. That is:

$$S_{sim}=\frac{\left|C_m\cap T_{\Delta }(C_n)\right|}{\max (\left|C_m\right|,\left|C_n\right|)}\ge \theta$$(7)

where S_sim is the similarity score. C_m and C_n represent the sets of hole positions for different modules. $T_{\Delta }(C_n)$ is the translation transformation operator, denoting the set of all hole coordinates of module n after applying the translation vector Δ. |·| is the operator that calculates the number of holes in a hole set. ∩ is the operator that computes the intersection of hole sets, i.e., the number of overlapping holes. θ is the similarity threshold. When the calculated similarity score is greater than or equal to the threshold θ, modules m and n are determined to be repeated modules.

3.2 Clustering algorithm

To fully leverage the known structural information in PCB design, this algorithm first adopts a deterministic clustering method based on predefined engineering parameters. This approach is based on the observation that in standardized PCB designs, drilling points are typically replicated and arranged in functional modules, with each module containing a fixed number of holes.

The clustering principle is as follows: Let the PCB board to be processed contain a total of n_total holes, which are designed as a rectangular array of n_module = N_x×N_y identical functional modules. The number of holes per standard module, n_holes can be calculated as n_holes = n_total / n_module. Assuming the storage order of the original hole position dataset reflects the design logic, the hole cluster C_m corresponding to the module m can be defined as:

$$C_m=\left\{v_i\in V|\lfloor \frac{i-1}{n_{holes}}\rfloor =m-1\right\},m=1,2,\dots ,n_{module}$$(8)

where $\lfloor \cdot \rfloor$ represents the floor function, and i is the index of the hole position in the original sequence. This formula divides the continuous sequence of hole indices into N_x×N_y equal-length segments through simple computation, with each segment corresponding to one module. Subsequently, the following completeness checks are performed:

$$\{\begin{array}{c}\left|C_j\right|=n_{holes}\\ C_m\cap C_n=\varnothing ,\forall m\ne n,{\cup }_{j=1}^{n_{module}}{C}_j=V\end{array}.$$(9)

If the verification passes, it indicates that the actual manufacturing data closely aligns with the design blueprint, and the process can proceed directly to the subsequent hierarchical optimization stage. This method leverages prior knowledge to simplify the large-scale clustering problem into a sequential partitioning problem, providing a rapid solution for handling ideal or approximately regular layouts. If the verification fails, the classical Density-Based Spatial Clustering of Applications with Noise (DBSCAN) algorithm is employed [16]. Ultimately, the original set of hole coordinates is output as a collection of fully partitioned, mutually exclusive hole clusters:

$$C=\left\{C_1,C_2\mathrm{...},C{n}_{module}\right\}.$$(10)

3.3 Hierarchical path planning for cluster-based optimization

Inter-zone optimization determine the optimal sequence for visiting these k clusters, with the goal of minimizing non-cutting travel time between clusters. To facilitate high-level planning, each cluster C_i is first abstracted into a representative point g_i. Common methods include the centroid point method and the entry/exit point method. The centroid point method calculates the average position of all holes in a cluster as its representative location. The entry/exit point method selects the start and end points of the internal path π_i of cluster C_i as representative points, which more accurately reflects the actual movement cost during path connections.

Intra-zone optimization is responsible for generating a locally optimal path for each independent cluster. Specifically, it finds the shortest closed path π_i that visits all holes in C_i exactly once and returns to the starting point. This path is represented as a sequence specifying the order of visiting holes within the cluster. The objective is to minimize the total internal path length L(π_i), which is mathematically expressed as:

$$\min L({\pi }_i)={\displaystyle \sum _{k=1}^{n_i-1}d(p_{i,{\pi }_i(k)},p_{i,{\pi }_i(k+1)})+d(p_{i,{\pi }_i(n_i)},p_{i,{\pi }_i(1)})}$$(11)

where the function d(a, b) represents the Euclidean distance between points a and b. Depending on the feature type of the cluster, different optimization strategies are applied. For clusters with regular features, deterministic patterns can be used for internal path planning without combinatorial optimization. For example, in an M × N rectangular array, a serpentine path is often an optimal or near-optimal choice, and its total length is a fixed value that can be directly calculated. For irregularly shaped clusters obtained through density-based clustering, traditional TSP solvers are required. Improved algorithms such as GA, SA, or ACO are employed to obtain high-quality approximate solutions within a reasonable time.

Path merging is the final step of the hierarchical planning process, which integrates all subpaths into a complete and executable global path. Following the optimal cluster visitation sequence Π obtained from inter-zone optimization, the internal paths of each cluster are sequentially connected. The global path is constructed as follows:

$$Pat{h}_{global}={\pi }_{\Pi (1)}\oplus {\pi }_{\Pi (2)}\oplus \dots \oplus {\pi }_{\Pi (k)}$$(12)

When connecting two clusters C_i and C_j, the path moves directly from the endpoint of π_i to the starting point of π_j. If the centroid abstraction method was previously used, the actual distance from the real exit point of C_i to the real entry point of C_j must be computed and incorporated into the global path. The final global drilling path generated by the algorithm is near-optimal within each cluster, and the sequence of movements between clusters is also optimal or near-optimal. As a result, a globally approximate optimal solution is achieved, while computational efficiency is improved by orders of magnitude compared to traditional global optimization methods.

4 Experimental simulation and result analysis

4.1 Experimental setup

The test data were randomly generated to create synthetic datasets with controllable layout and clustering features, enabling systematic validation of algorithm performance under different scenarios. Two distinct dataset types were constructed:

• An Ideal Layout Features dataset, as shown in Figure 2a, where holes exhibit strictly regular matrix distributions (e.g., rectangular or circular arrays) and are perfectly replicated from a single template without deviation, aimed at verifying the algorithm's ability to identify and utilize regular patterns under perfect conditions and to evaluate the theoretical optimality of intra-zone optimization strategies such as serpentine paths.

• A Non-ideal Layout Features dataset, as shown in Figure 2b, where global hole distribution incorporates certain randomness and intra-cluster positions are perturbed based on regular templates, resulting in imperfectly identical holes within clusters to better emulate real-world manufacturing tolerances or layout adjustments, used to assess the algorithm's robustness under noise and its adaptability in handling imperfect data during feature extraction and clustering.

In the experimental parameter configuration, the key parameters of the proposed hybrid optimization algorithm were specified in detail, including the clustering radius, neighborhood search range, and iteration count. Meanwhile, the ACO algorithm was selected as the primary baseline for comparison [17]. Its parameters, such as the heuristic factor and pheromone evaporation coefficient, were thoroughly tuned to ensure optimal performance, thereby guaranteeing the fairness and validity of the comparative experiments. The ACO parameters are as follows: the number of ants is set to 80, the maximum number of iterations is set to 200, the pheromone importance factor is set to 1.2, the heuristic information importance factor is set to 8.0, the pheromone evaporation rate is set to 0.15, the exploration probability is set to 0.7, the initial pheromone level is set to 10⁻⁵, and the number of elite ants is set to 5.

In the evaluation of algorithm performance, the following metrics are comprehensively adopted: Total Path Length, which refers to the total planar movement distance traveled by the drill bit to complete all hole processing; Computation Time, indicating the time consumed from data input to final path output; Optimization Rate, representing the percentage reduction in path length compared to baseline algorithms; and Convergence, used to assess the convergence speed and stability of iterative algorithms across multiple runs.

To more comprehensively evaluate the performance and robustness of the proposed algorithm, this study further constructs synthetic test datasets of multiple scales and multiple feature types. All data are randomly generated according to design specifications. For each parameter configuration, 20 instances are independently generated, and the mean and standard deviation are taken as the final results to support statistically significant performance comparisons. Three test sets small-scale, medium-scale, and large-scale are established. To simulate diverse layout characteristics in PCB design, four test sets with varying proportions of feature compositions are constructed to examine the algorithm adaptability under feature degradation conditions. The feature complexity settings are shown in Table 1.

Fig. 2 Layout features dataset.

4.2 Results and discussion

4.2.1 Ideal layout features

The experimental dataset consists of hole clusters arranged in a 5×3 rectangular array pattern. Each cluster contains 40 holes with completely identical distribution. Figure 3 illustrates the drilling path result obtained from one typical run of the ACO algorithm.

In the comparative experiments where the ACO algorithm was used as a benchmark, although it demonstrated good path coherence and final solution quality in regular array layouts, it still exhibits several limitations. Firstly, despite the superior total path length achieved, the algorithm converges relatively slowly, requiring approximately 60 iterations to stabilize, with a runtime of up to 128 s, indicating room for improvement in optimization efficiency. Secondly, the ACO algorithm is highly sensitive to parameter settings such as pheromone evaporation factor and heuristic weight. Parameter tuning heavily relies on prior experience and involves high computational costs. Moreover, the algorithm shows significant randomness during the iterative process. As illustrated in Figure 3b, from the 20th to the 60th iteration where the optimal solution was obtained, nearly 40 iterations did not yield noticeable performance improvements, reflecting its low efficiency in the later search stages and a tendency to become trapped in local regions.

Figure 4 shows the results of the proposed algorithm when all hole groups are completely identical.

The proposed algorithm generates a more regular drilling path, significantly reducing redundant movements and crossover, thereby improving drilling efficiency and path rationality. The convergence curve shows that the proposed algorithm achieves the optimal solution with significantly fewer iterations. In terms of overall performance, the total path length of the algorithm is 3004 mm, representing a 12% reduction compared to the ACO algorithm. The computation time is 24 s, only 18.8% of that required by the ACO algorithm. However, minor crossover phenomena still exist between global and local paths, suggesting that the current path planning has not yet reached global optimality.

The ACO algorithm for local path planning has been enhanced through the integration of an elite ant strategy and a 2-opt local optimization mechanism. In addition, to optimize the connection efficiency and reduce crossover between hole clusters, the selection of cluster entry and exit points follows these principles: after the high-level path planning determines the cluster visitation sequence, the point closest to the previous cluster's exit is selected as the entry point for the current cluster, while the point nearest to the next cluster's boundary is chosen as the exit point.

The experimental results of the improved algorithm are illustrated in Figure 5.

It shows that the optimized algorithm completely eliminates local path crossover phenomena and significantly improves the connection sequence between hole clusters, while maintaining a convergence speed almost identical to that of the original algorithm.

Repeated runs of the algorithm yield slightly varying results. A statistical comparison of the performance of different algorithms is presented in Table 2.

Fig. 3 ACO algorithm results of ideal layout features.

Fig. 4 Proposed algorithm results of ideal layout features.

Fig. 5 Optimized proposed algorithm results of ideal layout features.

4.2.2 Non-ideal layout features

Under normal circumstances, the hole groups of a PCB do not have ideal distribution characteristics and exhibit a certain degree of randomness. To verify the versatility of the algorithm, the generated dataset needs to have non-ideal features. The hole groups are not strictly in an array and each hole group is not a complete copy.

Figure 6 shows the ACO algorithm results.

The ant colony algorithm does not consider the layout characteristics of holes, so the path may jump back and forth between two hole groups, as shown in the lower left corner of Figure 6a. This unreasonable planning increases the total path length. Furthermore, the algorithm demonstrates slow convergence, requiring 45 iterations to reach the optimum, with a total runtime of 103 s.

Figure 7 shows the Optimized Proposed algorithm results.

Experimental results demonstrate that the proposed optimized algorithm generates a rational path layout with virtually no crossings. The total path length is 5569 mm, which is 11.1% shorter than the 6264 mm achieved by the ACO algorithm. Furthermore, the computational time is approximately 23 s, representing only 22.3% of the time required by the ACO algorithm.

Fig. 6 ACO algorithm results of non-ideal layout features.

Fig. 7 Optimized proposed algorithm results of non-ideal layout features.

4.2.3 Statistical comparison results of multiple test cases

Table 3 presents the performance comparison results between the proposed algorithm and the ACO baseline algorithm on test datasets of different scales and varying feature complexity.

Overall, the proposed algorithm significantly outperforms the ACO baseline across all test scenarios. Under ideal regular array layouts, the path length optimization is most pronounced, with optimization rates ranging from 11.6% to 13.3%. As the hole distribution becomes increasingly irregular, progressing from Regular Type to Hybrid Type and then to Random Type, the path optimization rate decreases, indicating that increased difficulty in feature extraction adversely affects algorithm performance. Nevertheless, the proposed algorithm maintains positive optimization effects in all cases. Notably, computation time is substantially reduced across all scenarios, remaining largely unaffected by the complexity of layout features.

4.2.4 Real industrial PCB case study

To further validate the effectiveness and robustness of the proposed algorithm in a real production environment, this study introduces actual PCB drilling production data, with its original layout shown in Figure 8a. The PCB board measures 120 mm × 80 mm, containing a total of 158 holes with a diameter of 1.2 mm, which account for the vast majority of all holes. Based on the machining parameters of the CNC machine tool, a 4 × 4 panelization scheme was adopted, resulting in a total of 2,528 holes, with the final layout illustrated in Figure 8b.

The path planning result obtained by the proposed algorithm is shown in Figure 9. It can be observed that the path planning essentially realizes the concept of hierarchical planning, with no path crossings and reuse of paths for identical hole groups. The total path length is 14,415 mm, and the computation time is 241 s. Compared with the baseline algorithm, which yields a total path length of 16,724 mm and a computation time of 1,370 s, the proposed algorithm achieves a 13.8% path optimization rate and an 82.4% reduction in computation time in this real PCB case. This demonstrates that the proposed method is not only applicable to controlled synthetic data environments but also effectively addresses complex hole distributions and engineering constraints in real manufacturing scenarios, exhibiting strong potential for industrial application.

Fig. 8 Real industrial PCB case.

Fig. 9 Optimized proposed algorithm results of real industrial PCB case.

5 Conclusion

This paper studies the path optimization problem in PCB hole drilling. Aiming at the layout characteristics of PCB hole position distribution, a hybrid path optimization algorithm with hierarchical planning is proposed. The algorithm first identifies regularly arranged hole groups and clusters them into macro-operation units, and then adopts a hierarchical optimization strategy of “inter-cluster first, intra-cluster second” to decompose the large-scale path planning problem into multiple sub-problems. Experimental results demonstrate that the proposed algorithm performs effectively for hole cluster distributions with distinct layout characteristics, achieving a 13.9% reduction in path length and an 81.5% reduction in computation time compared to the ACO baseline algorithm. Even for non-ideal hole cluster distributions, it still achieves an 11.1% shorter path length. Repeated experiments consistently yielded the same performance. In the real PCB case, the proposed algorithm achieved a 13.8% path optimization rate and an 82.4% reduction in computation time. The proposed algorithm exhibits superior path planning capability and computational efficiency across various hole cluster distribution types, offering a robust and practical solution for intelligent PCB drilling.

Funding

This work was supported by the Key Problems in Science and Technology of Henan Provincial under Grant 252102240115.

Conflicts of interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Data availability statement

Data will be made available on reasonable request.

Author contribution statement

Wei Yang: Writing – original draft. Jiannan Chen: Writing – review & editing. Pengfei Ji: Supervision

References

All Tables

All Figures

	Fig. 1 Algorithm framework diagram.
In the text

	Fig. 2 Layout features dataset.
In the text

	Fig. 3 ACO algorithm results of ideal layout features.
In the text

	Fig. 4 Proposed algorithm results of ideal layout features.
In the text

	Fig. 5 Optimized proposed algorithm results of ideal layout features.
In the text

	Fig. 6 ACO algorithm results of non-ideal layout features.
In the text

	Fig. 7 Optimized proposed algorithm results of non-ideal layout features.
In the text

	Fig. 8 Real industrial PCB case.
In the text

	Fig. 9 Optimized proposed algorithm results of real industrial PCB case.
In the text